The present invention relates to a test circuit for electronic device, and more particularly, to a test circuit for detecting a short circuit failure or open circuit failure of bus lines connecting plural semiconductor devices (IC, LSI) incorporated in the electronic device.
The open/short circuit test for checking defects, such as short circuits across bus lines, short circuits across input/output pins, open circuits of bus lines, disconnections between bus lines and input/output pins, etc., is usually conducted before shipment of electronic device. The test circuit for executing the open/short circuit test is often incorporated into a semiconductor device. One reason is, for example, in a Chip Size Package (CSP) such as a Ball Grid Array (BGA), the input/output pins do not appear outside the board after mounting the CSP on the board. It is then impossible to carry out the open/short circuit test required using a probe by bringing the probe into contact with the input/output pins.
The test circuit supplies a semiconductor device with specific test data through the bus lines that connect the semiconductor device and the test circuit. The test circuit determines if the data output from the semiconductor device is equal to the expected data, thereby detecting short circuits across the bus lines and open circuits of the bus lines.
Japanese Published Unexamined Patent Application No. 5-99980 discloses a method of testing electric device. As shown in FIG. 1, multiple semiconductor devices including a measured semiconductor device 1 containing a test circuit 1a, and a measuring semiconductor device 2 containing a receiving circuit 2a that receives signals from the test circuit 1a are mounted on a board. Input/output pins Pa1–Pan of the measured device 1 are connected to input/output pins Pb1–Pbn of the measuring device 2 through bus lines DB1–DBn. The test circuit 1a selects a specific input/output pin, for example, Pa1, outputs the data “1: H level” from the selected input/output pin Pa1, and outputs the data “0: L level” from the other, not selected, input/output pins Pa2–Pan.
If the expected value “1” is not detected at the input/output pin Pb1 of the measuring device 2, the test circuit 1a determines that the bus lines DB1–DBn connecting the input/output pins Pa1–Pan to Pb1–Pbn are open, or that the bus lines DB1–DBn are not connected with the input/output pins Pa1–Pan and Pb1–Pbn (detection open circuit failure). On the basis of the data from the remaining input/output pins, except for the specific input/output pin Pb1, if the logical value “1” is detected, it is determined that there is a short circuit across the detected input/output pins (Pa2–Pan, Pb2–Pbn) and the specific input/output pins Pa1, Pb1, or across the bus lines DB1–DBn. By selecting the input/output pins sequentially in accordance with their physical address, the test circuit 1a carries out the open circuit and short circuit tests for all of the input/output pins Pa1–Pan of the measured device 1.
In some electronic device, the bus lines DB1–DBn are in the floating state. In this case, even if the selected input/output pin has an open circuit failure, when the bus lines DB1–DBn have electric charges accumulated, the logical value of the input/output pins Pb1–Pbn of the measuring device 2 can possibly be set to the expected value “1”. In such a case, even though the selected input/output pin has the open circuit failure, it is determined to be normal. That is, the open is not detected.
When the input/output pins Pa1–Pan are sequentially selected in accordance with the physical address, the logical value of the input/output pins Pa1–Pan is sequentially set to “1” in accordance with the physical address. In this case, there is a possibility of charges remaining on the bus line of the previously selected input/output pin. When a specific input/output pin of the measuring device 2 is the input/output pin Pb1 or Pb2 precedent to Pb3, for example, the remaining charges can sometimes make the test circuit detect the logical value “1”, which is identical to the expected value of the input/output pin Pb3. In such a case, regardless of the input/output pins Pb1, Pb2 being correctly connected, they are determined as having a short circuit failure.
When the drive capability of the output driver (buffer) of the measured device 1 is high, even if the charges on the selected bus line DB3, for example, leak slightly, if the drive capability of the output driver is sufficiently high to overcome the leakage of the charges, the test circuit will detect the logical value “1”, which is the same as the expected value, at the input/output pin Pb3. That is, the input/output pins Pa3, Pb3, and the bus line DB3 are determined as normal.
However, if the drive capability of the output driver of the measuring device 2 is low, even if the measuring device 2 outputs the logical value “1”, if the drive capability of the output driver of the measuring device 2 is insufficient to cancel the leakage of the charges, the input/output pin Pa3 of the measured device 1 is supplied with the logical value “0”. Therefore, although the connection between the device 1 and device 2 is faulty, it is determined as normal; or in reverse, it is determined as a failure, although it is normal.
In order to prevent such errors, it is conceivable to bidirectionally transmit and receive data between the measured device 1 and the measuring device 2 when carry out the test using the test circuit 1a and the receiving circuit 2a. However, using the test circuit 1a and the receiving circuit 2a leads to increasing the circuit size of the device 1 and device 2.
FIG. 2 is a schematic diagram of a prior art semiconductor device 100 provided with a test circuit. The semiconductor device 100 has multiple input pads IN0–INn, multiple output pads DQ0–DQn, and a test input pad IN. The input pads IN0–INn are each connected to input buffers 281, and to an internal circuit 282 through internal bus lines BLin. The output pads DQ0–DQn are each connected to output buffers 283, and to the internal circuit 282 through internal bus lines BLout.
The input pads IN0–INn are connected to respective test circuits 285. The test circuits 285 receive test signals from an external device through the input pads IN0–INn. The test circuits 285 are also each connected to the single test input pad IN, and receive a test signal from the external device through the test input pad IN. The output pads DQ0–DQn are each connected to test-dedicated output circuits 286, and the test-dedicated output circuits 286 are each connected to the test circuits 285 through test-dedicated internal bus lines BLex.
The test circuits 285 receive the test signals from the external device through the input pads IN0–INn and test input pad IN, and supply detection signals to the test-dedicated output circuits 286 through the test-dedicated internal bus lines BLex. The test-dedicated output circuits 286 supply, in response to the detection signals, response signals to the external device through the output pads DQ0–DQn.
When the terminals of the CSP connected to the input pads IN0–INn and the test input pad IN are properly connected to the wiring of the board, the test circuits 285 receive the test signals, and deliver the detection signals. On the other hand, when the terminals are not properly connected (non-conductive), the test circuits 285 do not deliver the detection signals and the test-dedicated output circuits 286 do not output the response signals.
When the terminals of the CSP connected to the output pads DQ0–DQn are properly connected to the wiring of the board, the response signals from the test-dedicated output circuits 286 are supplied to the external device. On the other hand, when the terminals are not properly connected (non-conductive), the response signals from the test-dedicated output circuits 286 are not supplied to the external device. Thus, based on the presence of the response signals, the connection (continuity state) between the terminals of the CSP and the wiring of the board is determined.
However, the provision of the test circuits 285, test-dedicated output circuits 286, and test-dedicated internal bus lines BLex increases the circuit size of the semiconductor device.
Further, while a continuity test is carried out on one semiconductor device, if there is a continuity failure in another semiconductor device, on the basis of the continuity failure, the other semiconductor devices will be selected for testing. In this case, plural semiconductor devices operate simultaneously on the board, and bus contention is created on the board. Accordingly, it is necessary to regulate the operation of the semiconductor devices other than the device being tested.